1. Field of the Invention
This invention relates to an input/output port, and, in particular, to an input/output port device for use in a microcomputer, gate array, or the like.
2. Description of the Prior Art
In a microcomputer system or the like, use is typically made of an input/output port as an interface between a central processing unit or simply CPU and various input/output devices. One typical prior art input/output port is shown in FIG. 3. The input/output port shown in FIG. 3 includes a common input/output terminal P, which is commonly used for data input and for data output and to which is connected a first transistor Q.sub.1 for pull-up function and a second transistor Q.sub.2 for output function. The first transistor Q.sub.1 is comprised of a P-channel MOS transistor which has its source connected to a high level voltage source V.sub.DD, its drain connected to the common input/output terminal P and its gate connected to ground. The second transistor Q.sub.2 is comprised of an N-channel MOS transistor which has its drain connected to the common input/output terminal P and its source connected to a low level voltage source V.sub.SS (or ground GND in the illustrated example).
The mode of operation between data input and data output is designated by a data supplied to a data direction register 3 through a data bus DB. That is, if a data "1" is supplied into the data direction register 3, the register 3 establishes a data output designation condition by supplying a high level signal to the inverting input terminal of a NOR gate 7. Under this condition, the data on the data bus DB is temporarily stored in a port latch 4, which supplies a high level or low level signal depending on the data on the data bus DB to the non-inverting input terminal of the NOR gate 7. At the NOR gate 7, if the output from the data direction register 3 is high and the output from the port latch 4 is low, then the NOR gate 7 supplies a high level output to the gate of the second transistor Q.sub.2, thereby causing the second transistor Q.sub.2 to be turned on. On the other hand, if a data "0" is written into the data direction resister 3, whereby the register 3 establishes a data input designation condition, the output from the NOR gate 7 becomes low to render the second transistor Q.sub.2 turned off irrespective of the state of the output from the port latch 4. In this manner, the second transistor Q.sub.2 is turned on or off in accordance with the data supplied from the port latch 4 only when the data direction register 3 designates a data output mode. Thus, under this condition, the signal at the common input/output terminal P becomes low or high, whereby the common input/output terminal P effectively serves as an output terminal.
On the other hand, if the data direction register 3 designates the data input mode and thus its output is at low level, the second transistor Q.sub.2 is maintained to be turned off, so that the common input/output terminal P is maintained at high impedance condition, thereby effectively serving as an input terminal. Under this condition, data supplied to the common input/output terminal P from an external input/output device is lead onto the data bus DB via an input buffer 5.
The input/output port shown in FIG. 3 includes the first transistor Q.sub.1 for pull-up function, and, thus, during a data input mode, it allows to input data even from such an external input/output device which cannot by itself output a high level signal, such as an open drain output stage, However, when the common input/output terminal P is used as an input terminal, if the common input/output terminal P is shorted to ground through an external switch, there will be created a constant flow of current through the first transistor Q.sub.1, which causes a problem of increased power consumption. In order to limit the unnecessary current flowing through the first transistor Q.sub.1, it is only necessary to lower the capability or power of the first transistor Q.sub.1. For this purpose, use may be made of a transistor having a high internal impedance for the first transistor Q.sub.1. However, if use is made of a low power device for the first transistor Q.sub.1, the transition from the on-state to the off-state of the second transistor Q.sub.2, to which current is supplied through the first transistor Q.sub.1, becomes slower. That is, under this condition, when the common input/output terminal P is used as an output terminal, it takes time for the signal at the terminal P to change from its high level to low level, thereby creating another problem of a reduction in responsiveness.
FIG. 4 shows another prior art input/output port which is an improvement over the structure shown in FIG. 3. In the input/output port shown in FIG. 4, the gate of the first transistor Q.sub.1 is not connected to ground, and, instead, it is connected to receive an output from a NAND gate 6 which has its one input terminal connected to the data direction register 3 and its other input terminal connected to the port latch 4. With this structure, in the case when the common input/output terminal P is used as an input terminal, if a data "0" is written into the data direction register 3, thereby causing the output from the register 3 to be low level, or the output from the port latch 4 is forced to be low at level, the first transistor Q.sub.1 is maintained to be off, so that the unnecessary current flowing at the time when the terminal P is shorted to ground through an external switch is decreased. On the other hand, in the case where data is to be input using the common input/output terminal P as an input terminal, a data "1" is written into the data direction register 3, thereby causing the output from the register 3 to be high at level, and, at the same time the output from the port latch 4 is forced to be high level. Under this condition, the first transistor Q.sub.1 is turned on to provide a pull-up function, and, at the same time, the second transistor Q.sub.2 is maintained off.
However, also in the structure shown in FIG. 4, the problem of presence of unnecessary current during data input mode still remains. That is, if the power of each of the transistors Q.sub.1 and Q.sub.2 is set to be lower, the unnecessary current during data input mode can be made smaller; however, the transition from the high level to the low level at the terminal P while the common input/output terminal P is used as an output terminal becomes slower, thereby producing a problem of a reduction in responsiveness. On the other hand, if the power of each of the transistors Q.sub.1 and Q.sub.2 is increased, i.e., if the internal impedance of each of the transistors Q.sub.1 and Q.sub.2 is set lower, there is brought about an increase of unnecessary current during data input mode.